FPGA · STM32 · Pulsed Power
Discretized Voltage Control of an LTD
Sponsored by Nevada National Security Sites
A stage-aware controls architecture for selecting LTD cell configurations between pulses, then issuing deterministic triggers for programmable output-voltage levels.
- FPGA enable/disable control for cells 2–4, with cell 1 serving as the base-firing cell
- Common brick configuration within each stage and independent configuration from stage to stage
- Diagnostic/status monitoring, voltage selection, and STM32-to-FPGA communication

